The present invention relates to an information processing apparatus having an address expansion function, and in particular to its address expansion control operation.
Assuming that two possible widths of address handled in a data processing system, such as an instruction address and an operand address, are 24 bits and 31 bits, for example, an instruction for changing over the address width and linking an instruction and an operand to an address routine with the address width thus changed over is provided in a data processing apparatus. This instruction is hereafter referred to as an address mode changeover instruction or simply as a mode changeover instruction.
An information processing apparatus performing the processing of the mode changeover instruction in accordance with the prior art is proposed in JP-A-60-142742. In the information processing apparatus of JP-A-60-142742, there is provided a function in which, when a mode changeover instruction of branch type is to be executed, an instruction of a branch destination is fetched before completion of the execution stage of the mode changeover instruction. However, the operand fetch with the address mode changed over cannot be performed until the execution stage of the preceding instruction is completed. Further, the operand fetch of an instruction located at a branch destination or link destination must wait until the execution state of the mode changeover instruction is completed, resulting in a problem of delayed processing in the information processing apparatus. Operand fetch requests include an operand fetch request or a decode synchronization request synchronized to decoding of an instruction specifying a memory operand and a refetch request for performing operand fetch again some time later when the decode synchronization request is not accepted by a memory unit. In the prior art, however, there is not provided means for coping with the decode synchronization request and the refetch request when the operand of an instruction of a link destination is fetched in the execution of the mode changeover instruction of a branch type.